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loongson instruction set architecture (loongarch®) is a new isa developed by loongson technology, whose first version was published in 2020 and incorporates about 2000 instructions.

loongarch isa consists of a compulsory infrastructure and several optional extensions. it defines several standard extensions in the first version, including loongson binary translation (lbt) extension, loongson virtualization (lvz) extension, loongson simd (lsx) extension, and loongson advanced simd (asx) extension.

the fundamental design goal of loongarch is not only to establish an independent information technology ecosystem but also to be compatible with the large number of existing applications from other ecosystems, especially those based on the mainstream isas such as x86 and arm.

since 2020, all cpu products developed by loongson technology have been based on loongarch isa. the first loongarch isa cpu chip, ls3a5000, was announced in july 2021, which is a quad-core chip with a clock speed up to 2.3~2.5ghz.



modernity: incorporating advanced features of recently developed isa technologies to improve performance and energy efficiency.

compatibility: instructions, runtime environments, and system states are designed for highly efficient binary translation.

configurability: a refined base isa with optional standard extensions, such as vector, virtualization, and binary translation.

extensibility: sufficient instruction encoding spaces remained for the continuous extension of loongarch in the future.


visit github for:

1. loongarch reference manual - volume 1: basic architecture;

2. ;

3. .





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